## I. INTRODUCTION

Analog integrated circuits are key hardware components for building new multi-media system applications including internet-of-things (IoT), 5G communication, and self-driving cars [1]. To comply with the emerging trends, new design methodologies for analog integrated circuits that can improve the circuit performance while maintaining good cost and power efficiency are in high demand [2]. Design automation is an ultimate goal for analog integrated circuits, since this can significantly improve the design time and productivity. However, unlike digital integrated circuits, where the design procedure can be fully automated – most of the digital processing algorithms realized using MATLAB codes or hardware description language (HDL) can be directly converted into transistor level circuits within several hours (this is called top-down design), analog circuits have a lot of limitations for design automation. This is mainly due to the non-linear behavior of the transistors that are used as basic elements.

A typical analog circuit design procedure consists of two major steps that are circuit topology selection and transistor biasing. In case of MOS transistors, biasing is setting the transistor size, in other words the aspect ratio (W/L) where W and L are the width and length, and fixing the operating voltages including the gate-to-source voltage V_{GS} and drain-to-source voltage V_{DS}, and the current I_{D} so that the transistor properly operates in the desired operation region [3]. However, due to the non-linear current-voltage (I-V) characteristics of the transistor, transistor biasing heavily rely on the case-by-case experience of the circuit designer and the circuit simulator, which is not very systematic and time consuming.

In this work, in order to overcome the limitations of analog integrated circuit design, in particular reducing the design time, a transistor circuit model based design method that can represent the saturation region operation with linear circuit components is proposed. This is similar to the linear circuit model used for time-mode circuits [4] and image processing circuits [5], however the proposed model is more specialized for MOS transistors. Since the proposed design method can replace the non-linear transistor with a linear circuit model, biasing will be simple and straightforward compared to the conventional design method that deals with the transistor as it is. As a result, the proposed design method can systematically bias the transistors without heavily relying on the designer’s experience and the circuit simulator, which will reduce the design time as well. However, the proposed biasing scheme differs from the well-known g_{m}/I_{D} method which also use charts and tables obtained from pre-simulated transistor data, since the main objective of g_{m}/I_{D} is to optimize the circuit performance and power consumption instead of biasing the transistor [6]. In order to verify the proposed method, a single-ended folded cascade amplifier will be used as a biasing example, where the transistor sizes are set so that the desired operating point is achieved without using the circuit simulator.

## II. AUTOMATED BIASING SCHEME

This section will describe the automated transistor biasing method based on linearized transistor circuit model, where an actual amplifier circuit will be used as an example to verify the effectiveness of the proposed biasing scheme.

Fig. 1 shows the single-ended folded cascade amplifier that will be used as the biasing example. This amplifier circuit is widely used in a variety of applications including IoT [7]. Table 1 shows the design constraint where the W of each transistor will be set based on the proposed biasing method such that the transistors operate at the desired DC bias point (V_{DS} and V_{GS}). However, before biasing the transistors, in order to satisfy all the other design constraints, the value of I_{ss}, V_{B1}, V_{B2}, V_{B3}, and R_{D} should be determined.

The steering current I_{ss} is bounded by the power consumption P_{D} and the trans-conductance g_{m} which are given as

where V_{ov1} = V_{GS1} – V_{TH} and I_{1} = I_{ss}/2, since I_{1} = I_{2} and I_{ss} = I_{1} + I_{2}. As a result, I_{ss} is set to the smallest possible value 54uA. Next, the input common mode voltage V_{I,cm} and the fixed DC gate bias V_{B1}, V_{B2}, and V_{B3} are set based on the V_{DS} and V_{GS} requirement of each transistor. V_{I,cm} is set by V_{DD} and V_{GS1}. That is,

V_{B1} is obtained from the following relationship

Since the source of M_{4} is tied to GND, V_{B2} is given as

The gate bias voltages that satisfy the V_{DS} and V_{GS} requirement for each transistor are V_{I,cm} = 2.1V, V_{B1} = 1.2V, V_{B2} = 2V, and V_{B3} = 1V. Also, the value of R_{D} is obtained by

where V_{s2} is the source voltage of M_{2} which is given as

As a result, the value of R_{D} that meets the design constraint is 33.6kΩ.

The proposed transistor circuit model is a linear model that represents the strong inversion saturation region operation of the transistor, since most of the analog circuits are realized based on the saturation region operation. Fig. 2(a) shows the nmos transistor symbol, (b) the proposed circuit model, and (c) the I-V curve that shows the two operation regions. Depending on the value of V_{DS}, the operation region of the transistor can be divided into two regions - linear (V_{DS} < V_{ov}) and saturation (V_{DS} > V_{ov}) where V_{ov} is the boundary voltage that is equivalent to (V_{GS} – V_{TH}) where V_{TH} is the threshold voltage. Although the transistor is a non-linear device, the saturation region can be modeled with simple circuit components such as the current/voltage source and the resistor, since the saturation region current I_{D} has a linear relationship with V_{DS}. Therefore, the key ideal of the proposed transistor circuit model is to divide I_{D} into two components that are the active current I_{A} and the passive current I_{P}, which is represented by the left and right branch in the circuit model. In addition, I_{A} depends on V_{GS} and I_{P} is determined by V_{DS}, R_{out}, and V_{ov} where R_{out} is the saturation region output resistance. The expressions for I_{A} and I_{P} of the nmos are given as

Fig. 3 (a) shows the pmos transistor symbol. (b) the proposed circuit model, and (c) the I-V curve, where the circuit model is similar to the NMOS, except V_{GS}, V_{DS}, V_{ov}, and V_{TH} are negative, and the electron mobility μ_{n} will be replaced with hole mobility μ_{p}. The expressions for I_{A} and I_{P} of the pmos are given as

Once the V_{DS}, V_{GS}, and I_{D} of the transistors are determined, each transistor in the amplifier circuit will be replaced with the linearized transistor circuit model where W of the transistors are set based on the desired operating point – this is the biasing procedure. Toward this end, we will first find the passive current I_{P} based on eq. (8b) and (9b), and find the active current I_{A} using

However, to avoid heavily relying on the circuit simulator, curve fitted expressions obtained from the pre-simulated data of R_{out} and I_{A} will be used for finding I_{P} and W of each transistor. The pre-simulation data is obtained using Cadence Spectra mixed signal circuit simulator.

Fig. 4(a) and (b) show R_{out} vs. I_{D} for the nmos and pmos, where the dots indicate the pre-simulation data and the red line is the curve fitted plot obtained from power fit. The curve fitted expression for the nmos and pmos are given as

Using the above expressions, R_{out} at the desired bias current I_{D} can be obtained, where for M_{1}, M_{2}, M_{3}, I_{D} = I_{ss}/2 and for M_{4}, I_{D} = I_{ss}. In addition, Fig. 5(a) and (b) show I_{A} vs. W of the nmos (V_{GS} = 1V) and pmos (|V_{GS}| = 0.9V), where the dots indicate the pre-simulated data and the red line is the curved fitted plot obtained from linear fit. The curve fitted expressions for the nmos and pmos are given as:

Based on the above expressions, W corresponding to I_{A} can be obtained. This W will enable the transistor to operate at the desired V_{DS}, V_{GS}, and I_{D}. Table 2 shows the R_{out}, I_{P}, I_{A}, and W of each transistor obtained from the proposed biasing method, where a MATLAB program is used to compute R_{out}, I_{P}, I_{A}, and W. As shown, the proposed biasing method only use basic pre-simulation data for the nmos and pmos instead of heavily relying on the circuit simulator throughout the entire biasing steps, which can enable a faster design time. Furthermore, to show the effectiveness of the proposed biasing scheme, the same single-ended folded cascode amplifier (Fig. 1) has been biased with the conventional approach (mainly using the circuit simulator), where design (biasing) time of the proposed method showed 10× faster than the conventional method.

Transistor | R_{out} (kΩ) |
I_{P} (uA) |
I_{A} (uA) |
W (um) |
---|---|---|---|---|

M_{1} |
548 | 3.37 | 23.63 | 3.61 |

M_{2} |
548 | 0.82 | 26.18 | 3.98 |

M_{3} |
754 | 0.13 | 26.87 | 1.65 |

M_{4} |
516 | 1.16 | 52.84 | 3.30 |

## III. CONCLUSION

This work presents an automated transistor biasing scheme for analog integrated circuits based on the linearized transistor circuit model along with the curve fitted expressions obtained from the pre-simulated I-V characteristics of the transistor. As a result, the transistor size that leads to the desired operating point can be easily determined without heavily relying on the circuit sim-ulator, which leads to significant design time reduction. The proposed method is applied to an actual amplifier circuit where the design time based on the proposed biasing method showed 10× faster than the conventional design approach using the circuit simulator. As a future work, the proposed method will be applied to biasing different types of amplifiers.