Brief Paper: Linearized Transistor Model Based Automated Biasing Scheme for Analog Integrated Circuits

Lacek, Matthew; Nahra, Daniel; Roter, Ben; Lee, Kye-Shin

doi:10.33851/JMIS.2021.8.2.143

J Multimed Inf Syst 8(2):143-146

eISSN: 2383-7632

DOI: https://doi.org/10.33851/JMIS.2021.8.2.143

Section D

Brief Paper: Linearized Transistor Model Based Automated Biasing Scheme for Analog Integrated Circuits

Matthew Lacek¹, Daniel Nahra¹, Ben Roter¹, Kye-Shin Lee¹^,^*

Author Information & Copyright ▼

¹Department of Electrical and Computer Engineering, The University of Akron, Akron, Ohio 44325, USA

^*Corresponding Author: Kye-Shin Lee, The University of Akron, Akron, Ohio 44325, USA. +1-330-972-2996, klee3@uakron.edu.

© Copyright 2021 Korea Multimedia Society. This is an Open-Access article distributed under the terms of the Creative Commons Attribution Non-Commercial License (http://creativecommons.org/licenses/by-nc/4.0/) which permits unrestricted non-commercial use, distribution, and reproduction in any medium, provided the original work is properly cited.

Received: Jun 04, 2021; Revised: Jun 16, 2021; Accepted: Jun 17, 2021

Published Online: Jun 30, 2021

Abstract

This work presents an automated transistor biasing scheme for analog integrated circuits. In order to effectively bias the transistor at a desired operating point, the proposed method uses a linearized transistor circuit model along with the curve fitted expressions obtained from the pre-simulated I-V characteristics of the actual transistor. As a result, the transistor size that leads to the desired operating point can be easily determined without heavily relying on the circuit simulator, which will lead to significant design time reduction. Furthermore, the proposed method is applied to an actual amplifier circuit where the design time based on the proposed biasing method showed 10× faster than the conventional design approach using the circuit simulator.

Keywords: Automated transistor biasing; Linearized transistor circuit model; Pre-simulated I-V data

I. INTRODUCTION

Analog integrated circuits are key hardware components for building new multi-media system applications including internet-of-things (IoT), 5G communication, and self-driving cars [1]. To comply with the emerging trends, new design methodologies for analog integrated circuits that can improve the circuit performance while maintaining good cost and power efficiency are in high demand [2]. Design automation is an ultimate goal for analog integrated circuits, since this can significantly improve the design time and productivity. However, unlike digital integrated circuits, where the design procedure can be fully automated – most of the digital processing algorithms realized using MATLAB codes or hardware description language (HDL) can be directly converted into transistor level circuits within several hours (this is called top-down design), analog circuits have a lot of limitations for design automation. This is mainly due to the non-linear behavior of the transistors that are used as basic elements.

A typical analog circuit design procedure consists of two major steps that are circuit topology selection and transistor biasing. In case of MOS transistors, biasing is setting the transistor size, in other words the aspect ratio (W/L) where W and L are the width and length, and fixing the operating voltages including the gate-to-source voltage V_GS and drain-to-source voltage V_DS, and the current I_D so that the transistor properly operates in the desired operation region [3]. However, due to the non-linear current-voltage (I-V) characteristics of the transistor, transistor biasing heavily rely on the case-by-case experience of the circuit designer and the circuit simulator, which is not very systematic and time consuming.

In this work, in order to overcome the limitations of analog integrated circuit design, in particular reducing the design time, a transistor circuit model based design method that can represent the saturation region operation with linear circuit components is proposed. This is similar to the linear circuit model used for time-mode circuits [4] and image processing circuits [5], however the proposed model is more specialized for MOS transistors. Since the proposed design method can replace the non-linear transistor with a linear circuit model, biasing will be simple and straightforward compared to the conventional design method that deals with the transistor as it is. As a result, the proposed design method can systematically bias the transistors without heavily relying on the designer’s experience and the circuit simulator, which will reduce the design time as well. However, the proposed biasing scheme differs from the well-known g_m/I_D method which also use charts and tables obtained from pre-simulated transistor data, since the main objective of g_m/I_D is to optimize the circuit performance and power consumption instead of biasing the transistor [6]. In order to verify the proposed method, a single-ended folded cascade amplifier will be used as a biasing example, where the transistor sizes are set so that the desired operating point is achieved without using the circuit simulator.

II. AUTOMATED BIASING SCHEME

This section will describe the automated transistor biasing method based on linearized transistor circuit model, where an actual amplifier circuit will be used as an example to verify the effectiveness of the proposed biasing scheme.

2.1. Biasing example

Fig. 1 shows the single-ended folded cascade amplifier that will be used as the biasing example. This amplifier circuit is widely used in a variety of applications including IoT [7]. Table 1 shows the design constraint where the W of each transistor will be set based on the proposed biasing method such that the transistors operate at the desired DC bias point (V_DS and V_GS). However, before biasing the transistors, in order to satisfy all the other design constraints, the value of I_ss, V_B1, V_B2, V_B3, and R_D should be determined.

Fig. 1. Single-ended folded cascode amplifier.

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Table 1. Single-ended folded cascode amplifier design constraints.

Parameter	Value
Trans-conductance (g_m)	≥ 350uA/V
Power consumption (P_D)	≤ 480uW
Supply voltage (V_DD)	3V
Threshold voltage (V_TH)	0.59V (nmos), -0.75V (pmos)
V_GS	1V (nmos), 0.9V (pmos)
V_DS	\|V_DS1\| = 2V, \|V_DS2\| = 0.6V, V_DS3 = 0.5V, V_DS4 = 1V
W, L	L = 1un, 0.5um ≤ W ≤ 10um

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The steering current I_ss is bounded by the power consumption P_D and the trans-conductance g_m which are given as

P D = I S S ⋅ V D D

(1)

g m = 2 I 1 V o v 1

(2)

where V_ov1 = V_GS1 – V_TH and I₁ = I_ss/2, since I₁ = I₂ and I_ss = I₁ + I₂. As a result, I_ss is set to the smallest possible value 54uA. Next, the input common mode voltage V_I,cm and the fixed DC gate bias V_B1, V_B2, and V_B3 are set based on the V_DS and V_GS requirement of each transistor. V_I,cm is set by V_DD and V_GS1. That is,

V I, c m = V D D − | V G S 1 | .

(3)

V_B1 is obtained from the following relationship

V B 1 = V D S 4 + V D S 3 + | V D S 2 | − | V D S 2 | .

(4)

Since the source of M₄ is tied to GND, V_B2 is given as

V B 2 = V G S 3 + V D S 4 .

(5)

The gate bias voltages that satisfy the V_DS and V_GS requirement for each transistor are V_I,cm = 2.1V, V_B1 = 1.2V, V_B2 = 2V, and V_B3 = 1V. Also, the value of R_D is obtained by

R D = V D D − V S 2 I 2,

(6)

where V_s2 is the source voltage of M₂ which is given as

V S 2 = | V D S 2 | + V D S 3 + V D S 4 .

(7)

As a result, the value of R_D that meets the design constraint is 33.6kΩ.

2.2. Linearized transistor circuit model

The proposed transistor circuit model is a linear model that represents the strong inversion saturation region operation of the transistor, since most of the analog circuits are realized based on the saturation region operation. Fig. 2(a) shows the nmos transistor symbol, (b) the proposed circuit model, and (c) the I-V curve that shows the two operation regions. Depending on the value of V_DS, the operation region of the transistor can be divided into two regions - linear (V_DS < V_ov) and saturation (V_DS > V_ov) where V_ov is the boundary voltage that is equivalent to (V_GS – V_TH) where V_TH is the threshold voltage. Although the transistor is a non-linear device, the saturation region can be modeled with simple circuit components such as the current/voltage source and the resistor, since the saturation region current I_D has a linear relationship with V_DS. Therefore, the key ideal of the proposed transistor circuit model is to divide I_D into two components that are the active current I_A and the passive current I_P, which is represented by the left and right branch in the circuit model. In addition, I_A depends on V_GS and I_P is determined by V_DS, R_out, and V_ov where R_out is the saturation region output resistance. The expressions for I_A and I_P of the nmos are given as

I A = (12) μ n C o x (W L) (V G S − V T H) 2,

(8a)

I P = V D S − V o v R o u t, n .

(8b)

Fig. 2. (a) nmos transistor symbol. (b) linearized transistor circuit model. (c) I-V characteristic.

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Fig. 3 (a) shows the pmos transistor symbol. (b) the proposed circuit model, and (c) the I-V curve, where the circuit model is similar to the NMOS, except V_GS, V_DS, V_ov, and V_TH are negative, and the electron mobility μ_n will be replaced with hole mobility μ_p. The expressions for I_A and I_P of the pmos are given as

I A = (12) μ p C o x (W L) (| V G S | − | V T H |) 2,

(9a)

I P = | V D S | − | V o v | R o u t, p .

(9b)

Fig. 3. (a) pmos transistor symbol. (b) linearized transistor circuit model. (c) I-V characteristic.

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2.3. Proposed transistor biasing method

Once the V_DS, V_GS, and I_D of the transistors are determined, each transistor in the amplifier circuit will be replaced with the linearized transistor circuit model where W of the transistors are set based on the desired operating point – this is the biasing procedure. Toward this end, we will first find the passive current I_P based on eq. (8b) and (9b), and find the active current I_A using

I A = I D − I P

(10)

However, to avoid heavily relying on the circuit simulator, curve fitted expressions obtained from the pre-simulated data of R_out and I_A will be used for finding I_P and W of each transistor. The pre-simulation data is obtained using Cadence Spectra mixed signal circuit simulator.

Fig. 4(a) and (b) show R_out vs. I_D for the nmos and pmos, where the dots indicate the pre-simulation data and the red line is the curve fitted plot obtained from power fit. The curve fitted expression for the nmos and pmos are given as

R o u t, n (I D) ≈ 91.99 I D − 0.8259 + 2.079 × 105

(11a)

R o u t, p (I D) ≈ 91.11 I D − 0.8133 + 7.987 × 105

(11b)

Fig. 4. R_out vs. I_D (a) nmos. (b) pmos.

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Using the above expressions, R_out at the desired bias current I_D can be obtained, where for M₁, M₂, M₃, I_D = I_ss/2 and for M₄, I_D = I_ss. In addition, Fig. 5(a) and (b) show I_A vs. W of the nmos (V_GS = 1V) and pmos (|V_GS| = 0.9V), where the dots indicate the pre-simulated data and the red line is the curved fitted plot obtained from linear fit. The curve fitted expressions for the nmos and pmos are given as:

I A, n (W) ≈ 16.32 W − 5.971 × 10 − 8 .

(12a)

I A, p (W) ≈ 7.129 W − 1.709 × 10 − 6 .

(12b)

Fig. 5. I_A vs. W (a) nmos, V_GS = 1V. (b) pmos, |V_GS| = 0.9V.

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Based on the above expressions, W corresponding to I_A can be obtained. This W will enable the transistor to operate at the desired V_DS, V_GS, and I_D. Table 2 shows the R_out, I_P, I_A, and W of each transistor obtained from the proposed biasing method, where a MATLAB program is used to compute R_out, I_P, I_A, and W. As shown, the proposed biasing method only use basic pre-simulation data for the nmos and pmos instead of heavily relying on the circuit simulator throughout the entire biasing steps, which can enable a faster design time. Furthermore, to show the effectiveness of the proposed biasing scheme, the same single-ended folded cascode amplifier (Fig. 1) has been biased with the conventional approach (mainly using the circuit simulator), where design (biasing) time of the proposed method showed 10× faster than the conventional method.

Table 2. Biasing results obtained from the proposed method.

Transistor	R_out (kΩ)	I_P (uA)	I_A (uA)	W (um)
M₁	548	3.37	23.63	3.61
M₂	548	0.82	26.18	3.98
M₃	754	0.13	26.87	1.65
M₄	516	1.16	52.84	3.30

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III. CONCLUSION

This work presents an automated transistor biasing scheme for analog integrated circuits based on the linearized transistor circuit model along with the curve fitted expressions obtained from the pre-simulated I-V characteristics of the transistor. As a result, the transistor size that leads to the desired operating point can be easily determined without heavily relying on the circuit sim-ulator, which leads to significant design time reduction. The proposed method is applied to an actual amplifier circuit where the design time based on the proposed biasing method showed 10× faster than the conventional design approach using the circuit simulator. As a future work, the proposed method will be applied to biasing different types of amplifiers.

Acknowledgement

This work was supported by The University of Akron Faculty Research Fellowship program (FRC-2020).

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